The present invention relates to a semiconductor device, and particularly to a technology which is effective when applied to a semiconductor device in which a semiconductor chip formed with a switching transistor is sealed in a resin.
In recent years, to achieve the miniaturization and high-speed response of a power source circuit or the like, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) used in the power source circuit has become high frequency.
In particular, the CPU (Central Processing Unit), DSP (Digital Signal Processor), or the like of a desk-top personal computer, a note-type personal computer, a server, a game machine, or the like tends to be larger in current and higher in operating frequency. Accordingly, to allow a power MOSFET forming a non-insulated-type DC-DC converter for controlling the power source of the CPU or DSP to be adapted to the large current and the high operating frequency, the technical development thereof has been promoted.
A DC-DC converter widely used as an example of the power source circuit has a configuration in which a power MOSFET for high-side switch and a power MOSFET for low-side switch are coupled in series to each other. The power MOSFET for high-side switch has a switching function for controlling the DC-DC converter, while the power MOSFET for low-side switch has a switching function for synchronous rectification. The two power MOSFETs are alternately turned ON/OFF, while being synchronized, to thereby effect conversion of a power source voltage.
Japanese Unexamined Patent Publication No. 2002-314086 (Patent Document 1) discloses MOSFETs with sense terminals in which a sense pad is provided near the surface of the chip, and a sense portion as a sense terminal is arranged immediately under the sense pad. In order to solve the problem that a crack occurs in a chip due to the impact upon compression bonding of a bonding wire, this publication describes a technique in which a planar region where cells are not disposed is provided adjacent to the sense portion, and the sense pad electrode is provided thereover.
Japanese Unexamined Patent Publication No. 2008-17620 (Patent Document 2) describes a technique related to a semiconductor device in which first, second, and third semiconductor chips are mounted in one package. The first chip is a first power MOSFET, the second semiconductor chip is a second power MOSFET, and a third semiconductor chip includes a drive circuit for driving the first and second power MOSFETs.